Parser(3) User Contributed Perl Documentation Parser(3)NAMEHardware::Verilog::Parser - A complete grammar for parsing Verilog code
using perl
SYNOPSIS
use Hardware::Verilog::Parser;
$parser = new Hardware::Verilog::Parser;
$parser->Filename(@ARGV);
DESCRIPTION
This module defines the complete grammar needed to parse any Verilog
code. By overloading this grammar, it is possible to easily create
perl scripts which run through Verilog code and perform specific
functions.
For example, a Hierarchy.pm uses Hardware::Verilog::Parser to overload
the grammar rule for module instantiations. This single modification
will print out all instance names that occur in the file being parsed.
This might be useful for creating an automatic build script, or a
graphical hierarchical browser of a Verilog design.
This module is currently in alpha release. All code is subject to
change. Bug reports are welcome.
DSLI information:
D - Development Stage
a - alpha testing
S - Support Level
d - developer
L - Language used
p - perl only, no compiler needed, should be platform independent
I - Interface Style
O - Object oriented using blessed references and / or inheritance
AUTHOR
Copyright (C) 2000 Greg London All Rights Reserved.
This program is free software; you can redistribute it and/or modify it
under the same terms as Perl itself.
email contact: greg42@bellatlantic.net
SEE ALSO
Parse::RecDescent, version 1.77
perl(1).
perl v5.14.0 2011-06-19 Parser(3)
