PHC2SYS(8)PHC2SYS(8)NAMEphc2sys - synchronize two clocks
SYNOPSISphc2sys [ -wmqvx ] [ -d pps-device ] [ -s device ] [ -c device ] [ -O
offset ] [ -P kp ] [ -I ki ] [ -S step ] [ -F step ] [ -R update-rate ]
[ -N clock-readings ] [ -u summary-updates ] [ -n domain-number ] [ -l
print-level ]
DESCRIPTIONphc2sys is a program which synchronizes two clocks in the system. Typi‐
cally, it is used to synchronize the system clock to a PTP hardware
clock (PHC), which itself is synchronized by the ptp4l(8) program.
Two synchronization modes are supported, one uses a pulse per second
(PPS) signal provided by the source clock and the other mode reads time
from the source clock directly. Some clocks can be used in both modes,
the mode which will synchronize the slave clock with better accuracy
depends on hardware and driver implementation.
OPTIONS-d pps-device
Specify the PPS device of the master clock (e.g. /dev/pps0).
With this option the PPS synchronization mode is used instead of
the direct mode. As the PPS signal does not specify time and
only marks start of a second, the slave clock should be already
close to the correct time before phc2sys is started or the -s
option should be used too. This option can be used only with the
system clock as the slave clock.
-s device
Specify the master clock by device (e.g. /dev/ptp0) or interface
(e.g. eth0) or by name (e.g. CLOCK_REALTIME for the system
clock). When this option is used together with the -d option,
the master clock is used only to correct the offset by whole
number of seconds, which cannot be fixed with PPS alone.
-i interface
Performs the exact same function as -s for compatibility rea‐
sons. Previously enabled specifying master clock by network
interface. However, this can now be done using -s and this
option is no longer necessary. As such it has been deprecated,
and should no longer be used.
-c device
Specify the slave clock by device (e.g. /dev/ptp1) or interface
(e.g. eth1) or by name. The default is CLOCK_REALTIME (the sys‐
tem clock).
-P kp Specify the proportional constant of the PI controller. The
default is 0.7.
-I ki Specify the integral constant of the PI controller. The default
is 0.3.
-S step
Specify the step threshold of the PI controller. It is the maxi‐
mum offset that the controller corrects by changing the clock
frequency instead of stepping the clock. The clock is stepped on
start regardless of the option if the offset is larger than 100
nanoseconds (unless the -F option is used). The value of 0.0
disables stepping after the start. The default is 0.0.
-F step
Specify the step threshold applied only on the first update. It
is the maximum offset that is corrected by adjusting clock. The
value of 0.0 disables stepping on start. The default is
0.0000001 (100 nanoseconds).
-R update-rate
Specify the slave clock update rate when running in the direct
synchronization mode. The default is 1 per second.
-N phc-num
Specify the number of master clock readings per one slave clock
update. Only the fastest reading is used to update the slave
clock, this is useful to minimize the error caused by random
delays in scheduling and bus utilization. The default is 5.
-O offset
Specify the offset between the slave and master times in sec‐
onds. See TIME SCALE USAGE below.
-u summary-updates
Specify the number of clock updates included in summary statis‐
tics. The statistics include offset root mean square (RMS), max‐
imum absolute offset, frequency offset mean and standard devia‐
tion, and mean of the delay in clock readings and standard devi‐
ation. The units are nanoseconds and parts per billion (ppb). If
zero, the individual samples are printed instead of the statis‐
tics. The messages are printed at the LOG_INFO level. The
default is 0 (disabled).
-w Wait until ptp4l is in a synchronized state. If the -O option is
not used, also keep the offset between the slave and master
times updated according to the currentUtcOffset value obtained
from ptp4l and the direction of the clock synchronization.
-n domain-number
Specify the domain number used by ptp4l. The default is 0.
-x When a leap second is announced, don't apply it in the kernel by
stepping the clock, but let the servo correct the one-second
offset slowly by changing the clock frequency (unless the -S
option is used).
-l print-level
Set the maximum syslog level of messages which should be printed
or sent to the system logger. The default is 6 (LOG_INFO).
-m Print messages to the standard output.
-q Don't send messages to the system logger.
-h Display a help message.
-v Prints the software version and exits.
TIME SCALE USAGE
Ptp4l uses either PTP time scale or UTC (Coordinated Universal Time)
time scale. PTP time scale is continuous and shifted against UTC by a
few tens of seconds as PTP time scale does not apply leap seconds.
In hardware time stamping mode, ptp4l announces use of PTP time scale
and PHC is used for the stamps. That means PHC must follow PTP time
scale while system clock follows UTC. Time offset between these two is
maintained by phc2sys.
Phc2sys acquires the offset value either by reading it from ptp4l when
-w is in effect or from command line when -O is supplied. Failure to
maintain the correct offset can result in local system clock being off
some seconds to domain master system clock when in slave mode, or
incorect PTP time announced to the network in case the host is the
domain master.
EXAMPLES
The host is a domain master, PTP clock is synchronized to system clock
and the time offset is obtained from ptp4l. Phc2sys waits for ptp4l to
get at least one port in master or slave mode before starting the syn‐
chronization.
phc2sys-c /dev/ptp0 -s CLOCK_REALTIME -w
Same as above, time offset is provided on command line and phc2sys does
not wait for ptp4l.
phc2sys-c /dev/ptp0 -s CLOCK_REALTIME -O 35
The host is in slave mode, system clock is synchronized from PTP clock,
phc2sys waits for ptp4l and the offset is set automatically.
phc2sys-s /dev/ptp0 -w
Same as above, PTP clock id is read from the network interface, the
offset is provided on command line phc2sys does not wait.
phc2sys-s eth0 -O -35
SEE ALSOptp4l(8)linuxptp November 2012 PHC2SYS(8)
